Knowledge catalogue
arXiv:2605.09416v1 Announce Type: new Abstract: Hardware-aware training (HAT) is widely used to improve the robustness of neural networks on non-ideal AI accelerators, such as analog in-memory computi
arXiv:2605.10807v1 Announce Type: cross Abstract: The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor i
arXiv:2605.09581v1 Announce Type: new Abstract: This paper presents a hardware architecture that implements the Contrast Maximization (CM) algorithm in Field-Programmable Gate Array (FPGA) resources f
arXiv:2605.09055v1 Announce Type: cross Abstract: Recent agentic-robotics systems, from Code-asPolicies to modern vision-language-action (VLA) foundation models, presuppose that drivers, SDKs, or ROS-
arXiv:2604.05983v2 Announce Type: replace-cross Abstract: We present Arch (AI-native Register-transfer Clocked Hardware), a hardware description language for micro-architecture specification and AI-as
arXiv:2512.24086v2 Announce Type: replace Abstract: In video and image generation tasks, Diffusion Transformer (DiT) models incur extremely high computational costs due to attention mechanisms, which
arXiv:2610.00687v1 Announce Type: cross Abstract: Hardware-operable failures (HOFs) interrupt large language model (LLM) training but permit recovery on the same hardware without reset, repair, or rep
arXiv:2512.04705v3 Announce Type: replace-cross Abstract: The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also it
arXiv:2610.00207v1 Announce Type: cross Abstract: Due to limited support for intra-tensor heterogeneous precision in conventional accelerators, neural network quantization remains largely restricted t
arXiv:2610.12762v1 Announce Type: new Abstract: Hardware datasheets contain engineering specifications essential for component selection, system integration, and hardware compatibility verification. H
arXiv:2606.00735v1 Announce Type: cross Abstract: In distributed Mixture-of-Experts (MoE) inference, input-dependent token routing interacts with GPU performance variability to create persistent strag
arXiv:2610.07283v1 Announce Type: new Abstract: Analog hardware platforms offer the potential to reduce energy consumption over digital architectures, but in order to succeed, large-scale analog syste
arXiv:2610.07026v1 Announce Type: new Abstract: The Offline AI Modules workstream enables practical, low-power, and community-accessible deployment of voice-first AI systems that operate fully offline
arXiv:2610.02376v1 Announce Type: cross Abstract: Co-designing ML models and the accelerators that run them is an unusual reasoning task: architects must draw confident, high-stakes conclusions about
arXiv:2610.02241v1 Announce Type: cross Abstract: Mixture-of-Experts (MoE) architectures allow frontier language models to scale to trillions of parameters, but their deployment is constrained by mass
arXiv:2607.28451v1 Announce Type: new Abstract: Autonomous systems inevitably age, yet their artificial intelligence typically assumes hardware remains in its original condition. Batteries degrade, se
arXiv:2607.26464v1 Announce Type: cross Abstract: Physical Unified Device Architecture (PUDA) is an AI-native hardware harness for self-driving laboratories (SDLs). Rather than building a human-center
arXiv:2606.03517v1 Announce Type: cross Abstract: Training quantum neural networks (QNNs) on quantum hardware is currently bottlenecked by the cost of gradient estimation: standard parameter-shift met
arXiv:2609.34785v1 Announce Type: cross Abstract: Developing agents for hardware design and verification requires reliable correctness feedback. As a hardware specification may permit correct implemen
arXiv:2609.35587v1 Announce Type: new Abstract: GPU libraries such as CUTLASS expose tens of thousands of semantically equivalent kernels for a single operation, making exhaustive autotuning expensive
arXiv:2608.22378v1 Announce Type: cross Abstract: Systolic arrays (SAs) have emerged as prominent hardware accelerators for matrix operations in deep learning, while floating point number formats enab
arXiv:2607.20377v1 Announce Type: cross Abstract: Quantum-kernel methods encode a dataset's geometry in a Gram matrix, so learning claims on hardware kernels assume the intended geometry survives exec
arXiv:2604.03345v2 Announce Type: replace Abstract: Kolmogorov-Arnold Networks (KANs) have recently emerged as a powerful architecture for various machine learning applications. However, their unique
arXiv:2606.17102v2 Announce Type: replace-cross Abstract: Quantum computing promises transformative advances across science and industry, yet the physical hardware that enables these computations rema
arXiv:2605.15226v1 Announce Type: cross Abstract: We ask whether agentic AI systems built for software engineering transfer to realistic hardware engineering. Existing hardware LLM benchmarks isolate
arXiv:2604.23547v1 Announce Type: cross Abstract: Efficient hardware implementation of nonlinear activation functions is a crucial task in deploying artificial neural networks on resource-constrained
arXiv:2604.21952v1 Announce Type: cross Abstract: This work presents a multi-layered methodology for efficiently accelerating multimodal foundation models (MFMs). It combines hardware and software co-
arXiv:2604.09631v1 Announce Type: cross Abstract: As deep learning models are deployed on resource constrained edge platforms in autonomous driving systems, reli able knowledge of hardware behavior un
arXiv:2604.09565v1 Announce Type: cross Abstract: This paper introduces a unified, hardware-independent baremetal runtime architecture designed to enable high-performance machine learning (ML) inferen
arXiv:2609.30272v1 Announce Type: cross Abstract: We present extbf{ENAS}, a hardware-aware Neural Architecture Search (NAS) framework that combines a static feasibility check, a cell-based search spac
arXiv:2511.15323v2 Announce Type: replace-cross Abstract: Hardware synthesis is a key interface between high-level programs and accelerator designs. Modern FPGAs increasingly expose heterogeneity in r
arXiv:2609.13551v1 Announce Type: new Abstract: Static-image benchmarks do not capture the computational and temporal requirements of practical orchard video analytics. This study presents an end-to-e
arXiv:2608.26199v1 Announce Type: new Abstract: We ask whether AI agents powered by locally deployed large language models can reliably automate expert-defined hardware design workflows in an industry
arXiv:2608.13293v1 Announce Type: new Abstract: Edge AI deployment demands neural architectures that are simultaneously accurate, computationally efficient, and hardware-deployable - a challenge addre
arXiv:2608.12140v1 Announce Type: cross Abstract: Boosted decision trees (BDTs) are widely used in latency-critical applications, but efficient hardware deployment remains challenging. Existing design
arXiv:2606.27294v1 Announce Type: cross Abstract: Analog hardware platforms such as coupled oscillators and Analog Ising Machines naturally solve differential equations at a fraction of the energy cos
arXiv:2606.06510v1 Announce Type: cross Abstract: Conventional HPC dogma holds that native hardware FP64 silicon is the irreducible foundation of scientific computing -- the 'holy grail' of double-pre
arXiv:2601.18696v4 Announce Type: replace Abstract: Hardware trojans are malicious circuits which compromise the functionality and security of an integrated circuit (IC). These circuits are manufactur
arXiv:2605.01935v1 Announce Type: cross Abstract: Vision Mamba (ViM) models offer a compelling efficiency advantage over Transformers by leveraging the linear complexity of State Space Models (SSMs),
arXiv:2603.25719v2 Announce Type: replace-cross Abstract: We present an empirical study of how far general-purpose coding agents -- without hardware-specific training -- can optimize hardware designs
arXiv:2604.19993v1 Announce Type: cross Abstract: Complex-Valued Neural Networks (CVNNs) have significant advantages in handling tasks that involve complex numbers. However, existing CVNNs are unable
arXiv:2604.12079v1 Announce Type: cross Abstract: Traditional machine learning depends on high-precision arithmetic and near-ideal hardware assumptions, which is increasingly challenged by variability
arXiv:2609.17491v1 Announce Type: new Abstract: Unauthorized hardware replacement can preserve a wireless device's logical identity while altering its physical implementation, posing a challenge to ha
arXiv:2603.12440v2 Announce Type: replace-cross Abstract: GPU kernel optimization challenges LLMs beyond standard coding tasks, as it requires an understanding of hardware architecture, parallel compu
arXiv:2608.14709v1 Announce Type: cross Abstract: This demo presents real-time AI-based uplink channel-estimation inference using data collected from a hardware-in-the-loop 5G platform. The data-colle
arXiv:2608.02671v1 Announce Type: cross Abstract: Malware detection using Hardware Performance Counters (HPC) has emerged as a promising solution to improve the security of computing systems as a comp
arXiv:2607.01660v1 Announce Type: new Abstract: Hardware impairments in massive multiple-input multiple-output (MIMO) receivers introduce inter-symbol memory and inter-element coupling, severely degra
arXiv:2606.29636v1 Announce Type: cross Abstract: An important task in quantum computing is unitary circuit synthesis compatible with physical hardware constraints. This problem has a natural hybrid s
arXiv:2512.05402v2 Announce Type: replace-cross Abstract: Bitcoin mining hardware acquisition requires strategic timing due to volatile markets, rapid technological obsolescence, and protocol-driven r
arXiv:2605.04282v1 Announce Type: new Abstract: Visual SLAM is a core component of spatial computing systems, yet deploying learned local feature extractors on microcontroller-class hardware remains c
arXiv:2604.27911v1 Announce Type: new Abstract: Foundation models are deep neural networks (such as GPT-5, Gemini~3, and Opus~4) trained on large datasets that can perform diverse downstream tasks --
arXiv:2604.14709v2 Announce Type: replace Abstract: Existing benchmarks for hardware design primarily evaluate Large Language Models (LLMs) on isolated, component-level tasks such as generating HDL mo
arXiv:2609.36134v1 Announce Type: new Abstract: Functional Kolmogorov-Arnold Networks (FunKAN) achieve state-of-the-art accuracy on MRI Gibbs artifact removal and anatomical segmentation, but their 11
arXiv:2608.25570v1 Announce Type: new Abstract: Hardware kernel optimization requires repeated compilation, correctness testing, profiling, and revision. LLM agents can automate parts of this process,
arXiv:2601.08856v3 Announce Type: replace-cross Abstract: Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the s
arXiv:2608.09914v1 Announce Type: cross Abstract: Hardware assurance relies on scanning electron microscopy (SEM) to verify nanoscale structures, but assembling the large, high-quality datasets requir
arXiv:2608.01648v1 Announce Type: new Abstract: Hardware error logs in high-performance computing (HPC) systems provide early signals of abnormal behavior, yet there remain challenges in effectively f
arXiv:2607.26016v1 Announce Type: cross Abstract: Recently, photonic transformer accelerators (PTAs) have successfully achieved significant speedup and energy efficiency improvements over electronic a
arXiv:2607.06760v1 Announce Type: new Abstract: Autonomous systems under partial observability act on beliefs, not raw sensor events. QANTIS treats the quantum processor as a calibrated belief-update
arXiv:2607.04531v1 Announce Type: cross Abstract: Low-precision neural networks are attractive for resource-constrained hardware, but fixed-point arithmetic introduces failure modes that are often hid